340 lines
9.1 KiB
C
340 lines
9.1 KiB
C
/*
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* CCTL - ChipCon Tiny Loader
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* A 1KB serial bootloader for the CC1110/CC1111
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* Joby Taffey (c) 2012 <jrt-cctl@hodgepig.org>
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*
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* Derived from CC Bootloader
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* Fergus Noble (c) 2011
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*/
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#include <stdint.h>
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#include <cc1110.h>
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#include "cc1110-ext.h"
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// Flash write timer value:
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// FWT = 21000 * FCLK / (16 * 10^9)
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// For FCLK = 24MHz, FWT = 0x1F
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// For FCLK = 26MHz, FWT = 0x11
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#define FLASH_FWT 0x11
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// Address of flash controller data register
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#define FLASH_FWDATA_ADDR 0xDFAF
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#define RXFIFO_ELEMENTS 2048
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#define RXFIFO_SIZE (RXFIFO_ELEMENTS - 1)
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static __xdata uint8_t rxfifo[RXFIFO_SIZE];
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static uint8_t rxfifo_in;
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static uint8_t rxfifo_out;
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static __xdata struct cc_dma_channel dma0_config;
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static const __code uint8_t * __at (0x0000) flashp;
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__xdata uint8_t rambuf[1024];
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uint8_t page;
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static const char banner[] = {'\r', '\n', 'C', 'C', 'T', 'L', '\r', '\n'};
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struct cc_dma_channel
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{
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uint8_t src_high;
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uint8_t src_low;
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uint8_t dst_high;
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uint8_t dst_low;
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uint8_t len_high;
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uint8_t len_low;
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uint8_t cfg0;
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uint8_t cfg1;
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};
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#define DMA_CFG0_TRIGGER_FLASH 18
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#define DMA_CFG1_SRCINC_1 (1 << 6)
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#define DMA_CFG1_DESTINC_0 (0 << 4)
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#define DMA_CFG1_PRIORITY_HIGH (2 << 0)
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#define DMAARM_DMAARM0 (1 << 0)
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#define DMA_LEN_HIGH_VLEN_MASK (7 << 5)
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#define DMA_LEN_HIGH_VLEN_LEN (0 << 5)
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#define DMA_LEN_HIGH_VLEN_PLUS_1 (1 << 5)
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#define DMA_LEN_HIGH_VLEN (2 << 5)
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#define DMA_LEN_HIGH_VLEN_PLUS_2 (3 << 5)
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#define DMA_LEN_HIGH_VLEN_PLUS_3 (4 << 5)
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#define DMA_LEN_HIGH_MASK (0x1f)
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#define DMA_CFG0_WORDSIZE_8 (0 << 7)
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#define DMA_CFG0_WORDSIZE_16 (1 << 7)
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#define DMA_CFG0_TMODE_MASK (3 << 5)
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#define DMA_CFG0_TMODE_SINGLE (0 << 5)
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#define DMA_CFG0_TMODE_BLOCK (1 << 5)
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#define DMA_CFG0_TMODE_REPEATED_SINGLE (2 << 5)
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#define DMA_CFG0_TMODE_REPEATED_BLOCK (3 << 5)
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void flash_erase_page(void)
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{
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while (FCTL & FCTL_BUSY);
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FWT = FLASH_FWT;
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FADDRH = page << 1;
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FADDRL = 0x00;
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// Erase the page that will be written to
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FCTL |= FCTL_ERASE;
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__asm nop __endasm;
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// Wait for the erase operation to complete
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while (FCTL & FCTL_BUSY) {}
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}
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void flash_write_trigger(void)
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{
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// Enable flash write. Generates a DMA trigger. Must be aligned on a 2-byte
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// boundary and is therefore implemented in assembly.
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// p.s. if this looks a little crazy its because it is, sdcc doesn't currently
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// support explicitly specifying code alignment which would make this easier
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__asm
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.globl flash_write_trigger_instruction
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.globl flash_write_trigger_done
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; Put our trigger instruction in the HOME segment (shared with some startup code)
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; where it wont move around too much
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.area HOME (CODE)
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; Comment or uncomment these lines to adjust if you change the start.asm code
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nop ; Padding to get onto 16-bit boundary
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flash_write_trigger_instruction:
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orl _FCTL, #0x02 ; FCTL |= FCTL_ERASE
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nop ; Required, see datasheet.
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ljmp flash_write_trigger_done ; Jump back into our function
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; Meanwhile, back in the main CSEG segment...
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.area CSEG (CODE)
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; Jump to the trigger instruction
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ljmp flash_write_trigger_instruction
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flash_write_trigger_done:
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__endasm;
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}
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void flash_write(void)
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{
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// Setup DMA descriptor
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dma0_config.src_high = (((uint16_t)(__xdata uint16_t *)rambuf) >> 8) & 0x00FF;
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dma0_config.src_low = ((uint16_t)(__xdata uint16_t *)rambuf) & 0x00FF;
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dma0_config.dst_high = (FLASH_FWDATA_ADDR >> 8) & 0x00FF;
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dma0_config.dst_low = FLASH_FWDATA_ADDR & 0x00FF;
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dma0_config.len_high = DMA_LEN_HIGH_VLEN_LEN;
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dma0_config.len_high |= ((1024) >> 8) & DMA_LEN_HIGH_MASK;
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dma0_config.len_low = (1024) & 0x00FF;
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dma0_config.cfg0 = \
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DMA_CFG0_WORDSIZE_8 | \
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DMA_CFG0_TMODE_SINGLE | \
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DMA_CFG0_TRIGGER_FLASH;
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dma0_config.cfg1 = \
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DMA_CFG1_SRCINC_1 | \
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DMA_CFG1_DESTINC_0 | \
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DMA_CFG1_PRIORITY_HIGH;
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// Point DMA controller at our DMA descriptor
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DMA0CFGH = ((uint16_t)&dma0_config >> 8) & 0x00FF;
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DMA0CFGL = (uint16_t)&dma0_config & 0x00FF;
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// Waiting for the flash controller to be ready
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while (FCTL & FCTL_BUSY);
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// Configure the flash controller
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FWT = FLASH_FWT;
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FADDRH = (page << 1) & 0x3F;
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//FADDRL = 0;//(page << 9) & 0xFF; // reset value is 0x00
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// Arm the DMA channel, so that a DMA trigger will initiate DMA writing
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DMAARM |= DMAARM_DMAARM0;
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// Enable flash write - triggers the DMA transfer
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flash_write_trigger();
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// Wait for DMA transfer to complete
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while (!(DMAIRQ & DMAIRQ_DMAIF0));
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// Wait until flash controller not busy
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while (FCTL & (FCTL_BUSY | FCTL_SWBSY));
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// By now, the transfer is completed, so the transfer count is reached.
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// The DMA channel 0 interrupt flag is then set, so we clear it here.
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DMAIRQ &= ~DMAIRQ_DMAIF0;
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}
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uint8_t cons_getch(void)
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{
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if (rxfifo_in == rxfifo_out)
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return 0;
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page = rxfifo[rxfifo_out];
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if (rxfifo_out + 1 == RXFIFO_SIZE)
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rxfifo_out = 0;
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else
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rxfifo_out++;
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return 1;
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}
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void cons_putc(uint8_t ch)
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{
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U0DBUF = ch;
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while(!(U0CSR & U0CSR_TX_BYTE)); // wait for byte to be transmitted
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U0CSR &= ~U0CSR_TX_BYTE; // Clear transmit byte status
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}
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void uart0_isr(void) __interrupt URX0_VECTOR
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{
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URX0IF = 0;
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// HACK we know the buffer is big enough, as client is waiting for our ACK
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// if(rxfifo_in != (( rxfifo_out - 1 + RXFIFO_SIZE) % RXFIFO_SIZE)) // not full
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{
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rxfifo[rxfifo_in] = U0DBUF;
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if (rxfifo_in + 1 == RXFIFO_SIZE)
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rxfifo_in = 0;
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else
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rxfifo_in++;
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}
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}
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void jump_to_user(void)
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{
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if (*((__xdata uint8_t*)0x400) != 0xFF)
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{
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// Disable all interrupts
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EA = 0;
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IEN0 = IEN1 = IEN2 = 0;
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// bootloader not running
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F1 = 0;
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// Jump to user code
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__asm
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ljmp #0x400
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__endasm;
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}
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}
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void bootloader_main(void)
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{
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uint16_t i;
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uint8_t n;
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// Initialise clocks
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SLEEP &= ~SLEEP_OSC_PD; // enable RC oscillator
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while( !(SLEEP & SLEEP_XOSC_S) ); // let oscillator stabilise
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CLKCON = CLKCON_OSC32 | CLKCON_OSC | TICKSPD_DIV_32 | CLKSPD_DIV_2; // select internal HS RC oscillator
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while (!(CLKCON & CLKCON_OSC));
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CLKCON = CLKCON_OSC32 | TICKSPD_DIV_32 | CLKSPD_DIV_1; // select external crystal
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// while (CLKCON & CLKCON_OSC);
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// SLEEP |= SLEEP_OSC_PD; // Disable RC oscillator now that we have an external crystal
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rxfifo_in = rxfifo_out = 0;
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PERCFG = (PERCFG & ~PERCFG_U0CFG) | PERCFG_U1CFG;
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P0SEL |= (1<<3) | (1<<2);
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U0CSR = 0x80 | 0x40; // UART, RX on
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U0BAUD = 34; // 115200
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U0GCR = 13; // 115k2 baud at 13MHz, useful for coming out of sleep. Assumes clkspd_div2 in clkcon for HSRC osc
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URX0IF = 0; // No interrupts pending at start
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URX0IE = 1; // Serial Rx irqs enabled in system interrupt register
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F1 = 1;
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EA = 1;
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n = 0;
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while(n < sizeof(banner))
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cons_putc(banner[n++]);
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n = 8;
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i = 65535;
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while(!cons_getch() && n > 0)
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{
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if (i-- == 0)
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{
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cons_putc('B');
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n--;
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}
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}
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if (n != 0)
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goto upgrade_loop;
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jump_to_user();
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upgrade_loop:
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WDCTL = (WDCTL & ~WDCTL_INT) | WDCTL_INT_SEC_1; // watchdog on LS RCOSC, ~1s
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WDCTL = (WDCTL & ~WDCTL_MODE) | WDCTL_EN; // start
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while(1)
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{
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if (cons_getch())
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{
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WDCTL = (WDCTL & ~0xF0) | (0xA0); // pat
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WDCTL = (WDCTL & ~0xF0) | (0x50);
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switch(page)
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{
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case 'e':
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while(!cons_getch());
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flash_erase_page();
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goto ack;
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break;
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case 'p':
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while(!cons_getch());
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flash_write();
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goto ack;
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break;
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case 'r':
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while(!cons_getch());
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for (i=page<<10;i<(page+1)<<10;i++)
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cons_putc(flashp[i]);
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goto ack;
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break;
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case 'l':
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i = 0;
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while(i<1024)
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{
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while(!cons_getch());
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rambuf[i] = page;
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i++;
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}
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goto ack;
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break;
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case 'j':
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jump_to_user();
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break;
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ack:
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cons_putc(0);
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}
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}
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}
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}
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