re-add armStart.S and fix CMakeLists.txt
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Amrit Panesar committed
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@@ -61,8 +61,18 @@ add_executable( ${TARGET_BUILD}
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${rpiIncludes}
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)
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set_target_properties( ${TARGET_BUILD}
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PROPERTIES
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ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib"
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LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib"
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RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin"
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)
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get_target_property(RUNTIME_OUTPUT_DIRECTORY ${TARGET_BUILD} RUNTIME_OUTPUT_DIRECTORY)
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add_custom_command(
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TARGET ${TARGET_BUILD} POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} ${TARGET_BUILD} -O binary ${TARGET_OUTPUT}
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WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
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WORKING_DIRECTORY ${RUNTIME_OUTPUT_DIRECTORY}
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COMMENT "Convert the ELF output file to a binary image" )
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BIN
Binary file not shown.
BIN
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+163
@@ -0,0 +1,163 @@
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// Part of the Raspberry-Pi Bare Metal Tutorials
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// Copyright (c) 2013-2015, Brian Sidebotham
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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.section ".text.startup"
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.global _start
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.global _get_stack_pointer
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.global _exception_table
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.global _enable_interrupts
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// From the ARM ARM (Architecture Reference Manual). Make sure you get the
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// ARMv5 documentation which includes the ARMv6 documentation which is the
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// correct processor type for the Broadcom BCM2835. The ARMv6-M manuals
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// available on the ARM website are for Cortex-M parts only and are very
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// different.
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//
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// See ARM section A2.2 (Processor Modes)
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.equ CPSR_MODE_USER, 0x10
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.equ CPSR_MODE_FIQ, 0x11
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.equ CPSR_MODE_IRQ, 0x12
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.equ CPSR_MODE_SVR, 0x13
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.equ CPSR_MODE_ABORT, 0x17
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.equ CPSR_MODE_UNDEFINED, 0x1B
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.equ CPSR_MODE_SYSTEM, 0x1F
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// See ARM section A2.5 (Program status registers)
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.equ CPSR_IRQ_INHIBIT, 0x80
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.equ CPSR_FIQ_INHIBIT, 0x40
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.equ CPSR_THUMB, 0x20
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.equ SCTLR_ENABLE_DATA_CACHE, 0x4
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.equ SCTLR_ENABLE_BRANCH_PREDICTION, 0x800
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.equ SCTLR_ENABLE_INSTRUCTION_CACHE, 0x1000
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_start:
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ldr pc, _reset_h
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ldr pc, _undefined_instruction_vector_h
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ldr pc, _software_interrupt_vector_h
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ldr pc, _prefetch_abort_vector_h
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ldr pc, _data_abort_vector_h
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ldr pc, _unused_handler_h
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ldr pc, _interrupt_vector_h
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ldr pc, _fast_interrupt_vector_h
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_reset_h: .word _reset_
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_undefined_instruction_vector_h: .word undefined_instruction_vector
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_software_interrupt_vector_h: .word software_interrupt_vector
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_prefetch_abort_vector_h: .word prefetch_abort_vector
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_data_abort_vector_h: .word data_abort_vector
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_unused_handler_h: .word _reset_
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_interrupt_vector_h: .word interrupt_vector
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_fast_interrupt_vector_h: .word fast_interrupt_vector
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_reset_:
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// We enter execution in supervisor mode. For more information on
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// processor modes see ARM Section A2.2 (Processor Modes)
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mov r0, #0x8000
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mov r1, #0x0000
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ldmia r0!,{r2, r3, r4, r5, r6, r7, r8, r9}
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stmia r1!,{r2, r3, r4, r5, r6, r7, r8, r9}
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ldmia r0!,{r2, r3, r4, r5, r6, r7, r8, r9}
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stmia r1!,{r2, r3, r4, r5, r6, r7, r8, r9}
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// Initialise Stack Pointers ---------------------------------------------
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// We're going to use interrupt mode, so setup the interrupt mode
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// stack pointer which differs to the application stack pointer:
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mov r0, #(CPSR_MODE_IRQ | CPSR_IRQ_INHIBIT | CPSR_FIQ_INHIBIT )
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msr cpsr_c, r0
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mov sp, #0x7000
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// Switch back to supervisor mode (our application mode) and
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// set the stack pointer. Remember that the stack works its way
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// down memory, our heap will work it's way up from after the
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// application.
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mov r0, #(CPSR_MODE_SVR | CPSR_IRQ_INHIBIT | CPSR_FIQ_INHIBIT )
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msr cpsr_c, r0
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mov sp, #0x8000
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// Enable L1 Cache -------------------------------------------------------
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// R0 = System Control Register
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mrc p15,0,r0,c1,c0,0
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// Enable caches and branch prediction
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orr r0,#SCTLR_ENABLE_BRANCH_PREDICTION
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orr r0,#SCTLR_ENABLE_DATA_CACHE
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orr r0,#SCTLR_ENABLE_INSTRUCTION_CACHE
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// System Control Register = R0
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mcr p15,0,r0,c1,c0,0
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// Enable VFP ------------------------------------------------------------
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// r1 = Access Control Register
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MRC p15, #0, r1, c1, c0, #2
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// enable full access for p10,11
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ORR r1, r1, #(0xf << 20)
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// ccess Control Register = r1
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MCR p15, #0, r1, c1, c0, #2
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MOV r1, #0
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// flush prefetch buffer because of FMXR below
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MCR p15, #0, r1, c7, c5, #4
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// and CP 10 & 11 were only just enabled
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// Enable VFP itself
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MOV r0,#0x40000000
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// FPEXC = r0
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FMXR FPEXC, r0
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// The c-startup function which we never return from. This function will
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// initialise the ro data section (most things that have the const
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// declaration) and initialise the bss section variables to 0 (generally
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// known as automatics). It'll then call main, which should never return.
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bl _cstartup
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// If main does return for some reason, just catch it and stay here.
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_inf_loop:
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b _inf_loop
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_get_stack_pointer:
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// Return the stack pointer value
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str sp, [sp]
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ldr r0, [sp]
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// Return from the function
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mov pc, lr
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_enable_interrupts:
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mrs r0, cpsr
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bic r0, r0, #0x80
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msr cpsr_c, r0
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mov pc, lr
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