Allow unaligned load/store in QVM interpreter/x86 compiler
constructions like (dataMask & ~3) was used to protect against out-of-bound load/store when address is 4-byte closer to dataMask but at the same time it effectively cut low address bits for ALL load/store operations which is totally wrong in terms of conformance to ALLOWED (i.e. generated by q3lcc from C sources) low-level operations like packed binary data parsing
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@@ -790,7 +790,7 @@ qboolean ConstOptimize(vm_t *vm, int callProcOfsSyscall)
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return qtrue;
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case OP_STORE4:
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EmitMovEAXStack(vm, (vm->dataMask & ~3));
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EmitMovEAXStack(vm, vm->dataMask);
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#if idx64
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EmitRexString(0x41, "C7 04 01"); // mov dword ptr [r9 + eax], 0x12345678
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Emit4(Constant4());
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@@ -805,7 +805,7 @@ qboolean ConstOptimize(vm_t *vm, int callProcOfsSyscall)
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return qtrue;
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case OP_STORE2:
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EmitMovEAXStack(vm, (vm->dataMask & ~1));
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EmitMovEAXStack(vm, vm->dataMask);
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#if idx64
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Emit1(0x66); // mov word ptr [r9 + eax], 0x1234
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EmitRexString(0x41, "C7 04 01");
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@@ -1377,7 +1377,7 @@ void VM_Compile(vm_t *vm, vmHeader_t *header)
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case OP_STORE4:
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EmitMovEAXStack(vm, 0);
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EmitString("8B 54 9F FC"); // mov edx, dword ptr -4[edi + ebx * 4]
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MASK_REG("E2", vm->dataMask & ~3); // and edx, 0x12345678
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MASK_REG("E2", vm->dataMask); // and edx, 0x12345678
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#if idx64
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EmitRexString(0x41, "89 04 11"); // mov dword ptr [r9 + edx], eax
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#else
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@@ -1389,7 +1389,7 @@ void VM_Compile(vm_t *vm, vmHeader_t *header)
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case OP_STORE2:
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EmitMovEAXStack(vm, 0);
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EmitString("8B 54 9F FC"); // mov edx, dword ptr -4[edi + ebx * 4]
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MASK_REG("E2", vm->dataMask & ~1); // and edx, 0x12345678
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MASK_REG("E2", vm->dataMask); // and edx, 0x12345678
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#if idx64
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Emit1(0x66); // mov word ptr [r9 + edx], eax
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EmitRexString(0x41, "89 04 11");
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