From 07ff76a51504a4d26a0a6aea883f7bd0258560d2 Mon Sep 17 00:00:00 2001 From: Joby Taffey Date: Mon, 12 Mar 2012 00:21:27 +0000 Subject: [PATCH] CCHL, a hardware ChipCon programmer following swra124, running on CC1110. Follows (almost) same protocol as CCTL, so same client s/w runs on osx/linux/win --- Makefile | 8 +- README.markdown | 10 + cchl/Makefile | 45 ++ {boot => cchl}/cc1110-ext.h | 0 cchl/main.c | 416 ++++++++++++ cctl-prog/cctl-prog.c | 29 +- {boot => cctl}/Makefile | 0 cctl/cc1110-ext.h | 1283 +++++++++++++++++++++++++++++++++++ {boot => cctl}/main.c | 0 {boot => cctl}/start.asm | 0 10 files changed, 1785 insertions(+), 6 deletions(-) create mode 100644 cchl/Makefile rename {boot => cchl}/cc1110-ext.h (100%) create mode 100644 cchl/main.c rename {boot => cctl}/Makefile (100%) create mode 100644 cctl/cc1110-ext.h rename {boot => cctl}/main.c (100%) rename {boot => cctl}/start.asm (100%) diff --git a/Makefile b/Makefile index e89f099..587d3d8 100644 --- a/Makefile +++ b/Makefile @@ -1,8 +1,12 @@ all: - make -C boot + make -C cctl make -C cctl-prog + make -C cchl + make -C example_payload clean: - make -C boot clean + make -C cctl clean make -C cctl-prog clean + make -C cchl clean + make -C example_payload clean diff --git a/README.markdown b/README.markdown index 0faa262..214ab16 100644 --- a/README.markdown +++ b/README.markdown @@ -4,6 +4,8 @@ CC Tiny Loader CCTL is a serial bootloader for the Chipcon CC1110/CC1111 using only one 1KB page of flash. It allows update of the the microcontroller firmware over its serial port. +Included is CCHL, ChipCon Hardware Loader, an application which runs on the CC111x and can program a slave device over the ChipCon debug interface (http://focus.ti.com/lit/ug/swra124/swra124.pdf) + The bootloader consists of two components, a piece of firmware that is flashed onto the device and a utility for downloading code and manipulating the flash memory. The client program, `cctl-prog` runs on Linux, OSX/Darwin and Windows. @@ -138,6 +140,13 @@ The protocol is given in detail in http://focus.ti.com/lit/ug/swra124/swra124.pd (CCTL is placed in the flash using this protocol, it is different to the serial protocol). +If you have access to one of the devices below, you can bootstrap out of it, by programming CCHL into a CC1110. CCHL allows the CC1110 to program virgin chips over the debug interface. + +To reflash a slave device, connect P1_6 to DD, P1_5 to DC and P1_4 to RESET, load `cchl.hex` onto a CC1110 running CCTL and run `cctl-prog` using the `--passthrough` flag. Eg. to program the `cctl` bootloader into a device: + + `./cctl-prog -p -d /dev/ttyUSB0 -f cctl.hex` + + Official hardware programmer * TI's CC-Debugger http://www.ti.com/tool/cc-debugger (Windows only) @@ -152,6 +161,7 @@ Open source implementations of protcol * Teensy (C) https://github.com/jkerdels/open_imme/tree/master/tools/teensy-prog * Linux GPIO sysfs (C) https://github.com/ffainelli/cc2530prog + Building for Windows -------------------- diff --git a/cchl/Makefile b/cchl/Makefile new file mode 100644 index 0000000..ecd4d22 --- /dev/null +++ b/cchl/Makefile @@ -0,0 +1,45 @@ +CC = sdcc + +CFLAGS = --model-small --opt-code-speed + +# NOTE: code-loc should be the same as the value specified for +# USER_CODE_BASE in the bootloader! +LDFLAGS_FLASH = \ + --out-fmt-ihx \ + --code-loc 0x400 --code-size 0x8000 \ + --xram-loc 0xf000 --xram-size 0x1000 \ + --iram-size 0x100 + +ifdef DEBUG +CFLAGS += --debug +endif + +SRC = main.c + +ADB=$(SRC:.c=.adb) +ASM=$(SRC:.c=.asm) +LNK=$(SRC:.c=.lnk) +LST=$(SRC:.c=.lst) +REL=$(SRC:.c=.rel) +RST=$(SRC:.c=.rst) +SYM=$(SRC:.c=.sym) + +PROGS=cchl.hex +PCDB=$(PROGS:.hex=.cdb) +PLNK=$(PROGS:.hex=.lnk) +PMAP=$(PROGS:.hex=.map) +PMEM=$(PROGS:.hex=.mem) +PAOM=$(PROGS:.hex=) + +%.rel : %.c + $(CC) -c $(CFLAGS) -o$*.rel $< + +all: $(PROGS) + +cchl.hex: $(REL) Makefile + $(CC) $(LDFLAGS_FLASH) $(CFLAGS) -o cchl.hex $(REL) + +clean: + rm -f $(ADB) $(ASM) $(LNK) $(LST) $(REL) $(RST) $(SYM) + rm -f $(PROGS) $(PCDB) $(PLNK) $(PMAP) $(PMEM) $(PAOM) + diff --git a/boot/cc1110-ext.h b/cchl/cc1110-ext.h similarity index 100% rename from boot/cc1110-ext.h rename to cchl/cc1110-ext.h diff --git a/cchl/main.c b/cchl/main.c new file mode 100644 index 0000000..841c760 --- /dev/null +++ b/cchl/main.c @@ -0,0 +1,416 @@ +/* + * CCHL - ChipCon Hardware Loader + * A hardware programmer for the CC1110/CC1111 which runs on the CC1110/CC1111 + * Joby Taffey (c) 2012 + * + * Derived from: + * CC Bootloader + * Fergus Noble (c) 2011 + * + * Open IMME https://github.com/jkerdels/open_imme + * Jochen kerdels + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include +#include +#include "cc1110-ext.h" + + +// Connect the target CC1110 up as follows +#define DD P1_6 +#define DD_BIT BIT6 +#define DC P1_5 +#define DC_BIT BIT5 +#define RST P1_4 +#define RST_BIT BIT4 + +#define RXFIFO_ELEMENTS 2048 +#define RXFIFO_SIZE (RXFIFO_ELEMENTS - 1) +static __xdata uint8_t rxfifo[RXFIFO_SIZE]; +static uint8_t rxfifo_in; +static uint8_t rxfifo_out; +static const __code uint8_t * __at (0x0000) flashp; +__xdata uint8_t rambuf[1024]; +static uint8_t page; + +static const char banner[] = {'\r', '\n', 'C', 'C', 'H', 'L', '\r', '\n'}; + + +#define BIT0 1 +#define BIT1 2 +#define BIT2 4 +#define BIT3 8 +#define BIT4 16 +#define BIT5 32 +#define BIT6 64 +#define BIT7 128 + + +#define ST_CHIP_ERASE_DONE 0x80 +#define ST_PCON_IDLE 0x40 +#define ST_CPU_HALTED 0x20 +#define ST_POWER_MODE_0 0x10 +#define ST_HALT_STATUS 0x08 +#define ST_DEBUG_LOCKED 0x04 +#define ST_OSCILLATOR_STABLE 0x02 +#define ST_STACK_OVERFLOW 0x01 + +#define FLASHPAGE_SIZE 1024 +#define FLASH_WORD_SIZE 2 +#define WORDS_PER_FLASH_PAGE 512 + +#define nop() __asm nop __endasm; + +void delay (unsigned char n) +{ + unsigned char i = 0; + unsigned char j = 0; + + n <<= 1; + while (--n != 0) + while (--i != 0) + while (--j != 0) + nop(); +} + +static void send_byte(uint8_t ch) +{ + int8_t i; + P1DIR |= DD_BIT; // output + + for (i = 7; i >= 0; i--) + { + if (ch & (1 << i)) + DD = 1; + else + DD = 0; + DC = 1; + DC = 0; + } +} + +static uint8_t recv_byte(void) +{ + uint8_t ch = 0; + int8_t i; + + P1DIR &= ~DD_BIT; // input + + for (i = 7; i >= 0; i--) + { + DC = 1; + if (DD) + ch |= (1 << i); + DC = 0; + } + return ch; +} + + +static void dbg_init(void) +{ + P1DIR |= RST_BIT; + P1DIR |= DC_BIT; // DC + P1DIR |= DD_BIT; // DD + DD = 0; + + // send debug init sequence + RST = 0; + delay(1); + DC = 0; + delay(1); + DC = 1; + delay(1); + DC = 0; + delay(1); + DC = 1; + delay(1); + DC = 0; + delay(1); + RST = 1; + delay(1); +} + +static uint8_t read_status(void) +{ + send_byte(0x34); + return recv_byte(); +} + +static void dbg_mass_erase(void) +{ + send_byte(0x14); + recv_byte(); + while (!(read_status() & ST_CHIP_ERASE_DONE)); +} + +static uint8_t debug_instr_1(uint8_t in0) +{ + send_byte(0x55); + send_byte(in0); + return recv_byte(); +} + +static uint8_t debug_instr_2(uint8_t in0, uint8_t in1) +{ + send_byte(0x56); + send_byte(in0); + send_byte(in1); + return recv_byte(); +} + +static uint8_t debug_instr_3(uint8_t in0, uint8_t in1, uint8_t in2) +{ + send_byte(0x57); + send_byte(in0); + send_byte(in1); + send_byte(in2); + return recv_byte(); +} + +static void write_xdata_memory(uint16_t address, uint16_t count, const __xdata uint8_t *buf) +{ + int i; + debug_instr_3(0x90,address >> 8,address); + for (i = 0; i < count; ++i) { + debug_instr_2(0x74, buf[i]); + debug_instr_1(0xF0); + debug_instr_1(0xA3); + } +} + +static void set_pc(uint16_t address) +{ + debug_instr_3(0x02,address >> 8,address); +} + +static void cpu_resume(void) +{ + send_byte(0x4C); + recv_byte(); // ignore sent value +} + + + +static void read_code_memory(uint16_t address, + uint8_t bank, + uint16_t count, + __xdata uint8_t *outputData) +{ + int i; + if (address >= 0x8000) + address = (address & 0x7FFF) + (bank * 0x8000); + + debug_instr_3(0x75,0xC7,(bank * 16) + 1); + debug_instr_3(0x90,address >> 8,address); + for (i = 0; i < count; ++i) { + debug_instr_1(0xE4); + outputData[i] = debug_instr_1(0x93); + debug_instr_1(0xA3); + } +} + +static __xdata uint8_t updProc[] = +{ + 0x75, 0xAD, /*ADDRESS*/0x00, + 0x75, 0xAC, 0x00, + 0x75, 0xAB, 0x23, 0x00, + 0x75, 0xAE, 0x01, // ------ + 0xE5, 0xAE, // erase code + 0x20, 0xE7, 0xFB, // ------ + 0x90, 0xF0, 0x00, + 0x7F, WORDS_PER_FLASH_PAGE >> 8, + 0x7E, WORDS_PER_FLASH_PAGE & 0xFF, + 0x75, 0xAE, 0x02, + 0x7D, FLASH_WORD_SIZE, + 0xE0, + 0xA3, + 0xF5, 0xAF, + 0xDD, 0xFA, + 0xE5, 0xAE, + 0x20, 0xE6, 0xFB, + 0xDE, 0xF1, + 0xDF, 0xEF, + 0xA5 +}; + + +static void write_flash_page(uint32_t address) +{ + uint8_t updProcSize = sizeof(updProc); + + updProc[2] = ((address >> 8) / FLASH_WORD_SIZE) & 0x7E; + + write_xdata_memory(0xF000, FLASHPAGE_SIZE, rambuf); + write_xdata_memory(0xF000 + FLASHPAGE_SIZE, updProcSize, updProc); + debug_instr_3(0x75,0xC7,0x51); + set_pc(0xF000 + FLASHPAGE_SIZE); + cpu_resume(); + while (!(read_status() & ST_CPU_HALTED)); +} + + + +static void read_flash_page(uint32_t address, __xdata uint8_t *outputData) +{ + read_code_memory(address & 0xFFFF, + (address >> 15) & 0x03, FLASHPAGE_SIZE, outputData); +} + + +static void dbg_readpage(void) +{ + read_flash_page(page * 1024, rambuf); +} + +static void dbg_writepage(void) +{ + uint32_t addr = page*1024; + write_flash_page(addr); +} + + + +uint8_t cons_getch(void) +{ + if (rxfifo_in == rxfifo_out) + return 0; + page = rxfifo[rxfifo_out]; + if (rxfifo_out + 1 == RXFIFO_SIZE) + rxfifo_out = 0; + else + rxfifo_out++; + return 1; +} + +void cons_putc(uint8_t ch) +{ + U0DBUF = ch; + while(!(U0CSR & U0CSR_TX_BYTE)); // wait for byte to be transmitted + U0CSR &= ~U0CSR_TX_BYTE; // Clear transmit byte status +} + +void uart0_isr(void) __interrupt URX0_VECTOR +{ + URX0IF = 0; + +// HACK we know the buffer is big enough, as client is waiting for our ACK +// if(rxfifo_in != (( rxfifo_out - 1 + RXFIFO_SIZE) % RXFIFO_SIZE)) // not full + { + rxfifo[rxfifo_in] = U0DBUF; + if (rxfifo_in + 1 == RXFIFO_SIZE) + rxfifo_in = 0; + else + rxfifo_in++; + } +} + +void main(void) +{ + uint16_t i; + uint8_t n; + + // Initialise clocks + SLEEP &= ~SLEEP_OSC_PD; // enable RC oscillator + while( !(SLEEP & SLEEP_XOSC_S) ); // let oscillator stabilise + + CLKCON = CLKCON_OSC32 | CLKCON_OSC | TICKSPD_DIV_32 | CLKSPD_DIV_2; // select internal HS RC oscillator + while (!(CLKCON & CLKCON_OSC)); + + CLKCON = CLKCON_OSC32 | TICKSPD_DIV_32 | CLKSPD_DIV_1; // select external crystal + +// while (CLKCON & CLKCON_OSC); +// SLEEP |= SLEEP_OSC_PD; // Disable RC oscillator now that we have an external crystal + + rxfifo_in = rxfifo_out = 0; + + PERCFG = (PERCFG & ~PERCFG_U0CFG) | PERCFG_U1CFG; + P0SEL |= (1<<3) | (1<<2); + U0CSR = 0x80 | 0x40; // UART, RX on + U0BAUD = 34; // 115200 + U0GCR = 13; // 115k2 baud at 13MHz, useful for coming out of sleep. Assumes clkspd_div2 in clkcon for HSRC osc + URX0IF = 0; // No interrupts pending at start + URX0IE = 1; // Serial Rx irqs enabled in system interrupt register + + EA = 1; + + n = 0; + while(n < sizeof(banner)) + cons_putc(banner[n++]); + + dbg_init(); + + i = 0; + while(!cons_getch()) + { + if (i-- == 0) + { + cons_putc('P'); + } + } + + while(1) + { + if (cons_getch()) + { + switch(page) + { + case 'e': + while(!cons_getch()); + dbg_mass_erase(); + goto ack; + break; + + case 'p': + while(!cons_getch()); + dbg_writepage(); + goto ack; + break; + + case 'r': + while(!cons_getch()); + dbg_readpage(); + for (i=0;i<1024;i++) + cons_putc(rambuf[i]); + goto ack; + break; + + case 'l': + i = 0; + while(i<1024) + { + while(!cons_getch()); + rambuf[i] = page; + i++; + } + goto ack; + break; + + case 'j': + WDCTL = (WDCTL & ~WDCTL_INT) | WDCTL_INT_SEC_1; // watchdog on LS RCOSC, ~1s + WDCTL = (WDCTL & ~WDCTL_MODE) | WDCTL_EN; // start + while(1); // reset + break; + + ack: + cons_putc(0); + } + } + } +} + + + diff --git a/cctl-prog/cctl-prog.c b/cctl-prog/cctl-prog.c index 948c012..3b3f82a 100644 --- a/cctl-prog/cctl-prog.c +++ b/cctl-prog/cctl-prog.c @@ -34,6 +34,7 @@ static struct option long_options[] = {"flash", required_argument, 0, 'f'}, {"device", required_argument, 0, 'd'}, {"timeout", required_argument, 0, 't'}, + {"passthrough", no_argument, 0, 'p'}, {0, 0, 0, 0} }; @@ -49,6 +50,7 @@ void usage(void) fprintf(stderr, " --console -c Connect console to serial port on device\n"); fprintf(stderr, " --flash=file.hex -f file.hex Reflash device with intel hex file\n"); fprintf(stderr, " --timeout=n -t n Search for bootload string for n seconds\n"); + fprintf(stderr, " --passthrough -p Program remote device over passthrough\n"); } static bool opt_console = false; @@ -57,6 +59,7 @@ static int opt_timeout = 10; static bool opt_device = false; static char *flash_filename = NULL; static char *device_name = NULL; +static bool opt_passthrough = 0; #ifndef WIN32 static struct termios orig_termios; @@ -69,7 +72,7 @@ int parse_options(int argc, char **argv) while(1) { - c = getopt_long (argc, argv, "hcf:d:t:", long_options, &option_index); + c = getopt_long (argc, argv, "hcf:d:t:p", long_options, &option_index); if (c == -1) break; switch(c) @@ -77,6 +80,9 @@ int parse_options(int argc, char **argv) case 'h': return 1; break; + case 'p': + opt_passthrough = 1; + break; case 't': opt_timeout = atoi(optarg); break; @@ -352,11 +358,15 @@ int read_page(int fd, uint8_t page, uint8_t *data) return 0; } +static int already_erased = 0; // passthrough programmer only supports mass erase int erase_page(int fd, uint8_t page) { char cmd = 'e'; char rsp; + if (already_erased && opt_passthrough) + return 0; + if (serialWrite(fd, &cmd, 1) <= 0) return 1; @@ -369,6 +379,8 @@ int erase_page(int fd, uint8_t page) return 1; } + already_erased = 1; + return 0; } @@ -457,7 +469,8 @@ int wait_for_bootloader(int fd, int timeout) gettimeofday(&start, NULL); - serialWrite(fd, "+++", 3); + if (!opt_passthrough) + serialWrite(fd, "+++", 3); printf("Waiting %ds for bootloader, reset board now\n", timeout); @@ -479,8 +492,16 @@ int wait_for_bootloader(int fd, int timeout) else if (rc == 1) { - if (c == 'B' && prev_c == 'B') - break; + if (opt_passthrough) + { + if (c == 'P' && prev_c == 'P') + break; + } + else + { + if (c == 'B' && prev_c == 'B') + break; + } prev_c = c; } } diff --git a/boot/Makefile b/cctl/Makefile similarity index 100% rename from boot/Makefile rename to cctl/Makefile diff --git a/cctl/cc1110-ext.h b/cctl/cc1110-ext.h new file mode 100644 index 0000000..5fec807 --- /dev/null +++ b/cctl/cc1110-ext.h @@ -0,0 +1,1283 @@ +/* + Filename: ioCCxx10_bitdef.h + + This file contains the bit definitions of registers in CCxx10 + + Copyright 2008 Texas Instruments, Inc. +*/ +#ifndef _IOCCXX10_BITDEF_H +#define _IOCCXX10_BITDEF_H + + + +/* SEE DATA SHEET FOR DETAILS ABOUT THE FOLLOWING BIT MASKS */ + + + +/* + * Memory Control Registers + */ + +// MPAGE (0x93) - Memory Page Select + +// MEMCTR (0xC7) - Memory Arbiter Control +#define MEMCTR_CACHD 0x02 +#define MEMCTR_PREFD 0x01 + + +/* + * CPU Registers + */ + +// DPH0 (0x83) - Data Pointer 0 High Byte + +// DPL0 (0x82) - Data Pointer 0 Low Byte + +// DPH1 (0x85) - Data Pointer 1 High Byte + +// DPL1 (0x84) - Data Pointer 1 Low Byte + +// DPS (0x92) - Data Pointer Select +#define DPS_VDPS 0x01 + + +// PSW (0xD0) - Progrttus Word - bit accessible SFR register + +// ACC (0xE0) - Accumulator - bit accessible SFR register + +// B (0xF0) - B Register - bit accessible SFR register + +// SP (0x81) - Stack Pointer + + +/* + * Interrupt Control Registers + */ + +// IEN0 (0xA8) - Interrupt Enable 0 Register - bit accessible SFR register + +// IEN1 (0xB8) - Interrupt Enable 1 Register - bit accessible SFR register +#define IEN1_T2IE 0x04 + +// IEN2 (0x9A) - Interrupt Enable 2 Register +#define IEN2_WDTIE 0x20 +#define IEN2_P1IE 0x10 +#define IEN2_UTX1IE 0x08 +#define IEN2_I2STXIE 0x08 +#define IEN2_UTX0IE 0x04 +#define IEN2_P2IE 0x02 +#define IEN2_USBIE 0x02 +#define IEN2_RFIE 0x01 + + +// TCON (0x88) - CPU Interrupt Flag 1 - bit accessible SFR register + +// S0CON (0x98) - CPU Interrupt Flag 2 - bit accessible SFR register + +// S1CON (0x9B) - CPU Interrupt Flag 3 +#define S1CON_RFIF_1 0x02 +#define S1CON_RFIF_0 0x01 + + +// IRCON (0xC0) - CPU Interrupt Flag 4 - bit accessible SFR register + +// IRCON2 (0xE8) - CPU Interrupt Flag 5 - bit accessible SFR register + +// IP1 (0xB9) - Interrupt Priority 1 +#define IP1_IPG5 0x20 +#define IP1_IPG4 0x10 +#define IP1_IPG3 0x08 +#define IP1_IPG2 0x04 +#define IP1_IPG1 0x02 +#define IP1_IPG0 0x01 + +// IP0 (0xA9) - Interrupt Priority 0 +#define IP0_IPG5 0x20 +#define IP0_IPG4 0x10 +#define IP0_IPG3 0x08 +#define IP0_IPG2 0x04 +#define IP0_IPG1 0x02 +#define IP0_IPG0 0x01 + + + +/* + * Power Management and Clocks + */ + +// PCON (0x87) - Power Mode Control +#define PCON_IDLE 0x01 + + +// SLEEP (0xBE) - Sleep Mode Control +#define SLEEP_USB_EN 0x80 +#define SLEEP_XOSC_S 0x40 +#define SLEEP_HFRC_S 0x20 +#define SLEEP_RST 0x18 +#define SLEEP_RST0 0x08 +#define SLEEP_RST1 0x10 +#define SLEEP_OSC_PD 0x04 +#define SLEEP_MODE 0x03 +#define SLEEP_MODE1 0x02 +#define SLEEP_MODE0 0x01 + +#define SLEEP_RST_POR_BOD (0x00 << 3) +#define SLEEP_RST_EXT (0x01 << 3) +#define SLEEP_RST_WDT (0x02 << 3) + +#define SLEEP_MODE_PM0 (0x00) +#define SLEEP_MODE_PM1 (0x01) +#define SLEEP_MODE_PM2 (0x02) +#define SLEEP_MODE_PM3 (0x03) + + +// CLKCON (0xC6) - Clock Control +#define CLKCON_OSC32 0x80 // bit mask, for the slow 32k clock oscillator +#define CLKCON_OSC 0x40 // bit mask, for the system clock oscillator +#define CLKCON_TICKSPD 0x38 // bit mask, for timer ticks output setting +#define CLKCON_TICKSPD0 0x08 // bit mask, for timer ticks output setting +#define CLKCON_TICKSPD1 0x10 // bit mask, for timer ticks output setting +#define CLKCON_TICKSPD2 0x20 // bit mask, for timer ticks output setting +#define CLKCON_CLKSPD 0x07 // bit mask, for the clock speed +#define CLKCON_CLKSPD0 0x01 // bit mask, for the clock speed +#define CLKCON_CLKSPD1 0x02 // bit mask, for the clock speed +#define CLKCON_CLKSPD2 0x04 // bit mask, for the clock speed + +#define TICKSPD_DIV_1 (0x00 << 3) +#define TICKSPD_DIV_2 (0x01 << 3) +#define TICKSPD_DIV_4 (0x02 << 3) +#define TICKSPD_DIV_8 (0x03 << 3) +#define TICKSPD_DIV_16 (0x04 << 3) +#define TICKSPD_DIV_32 (0x05 << 3) +#define TICKSPD_DIV_64 (0x06 << 3) +#define TICKSPD_DIV_128 (0x07 << 3) + +#define CLKSPD_DIV_1 (0x00) +#define CLKSPD_DIV_2 (0x01) +#define CLKSPD_DIV_4 (0x02) +#define CLKSPD_DIV_8 (0x03) +#define CLKSPD_DIV_16 (0x04) +#define CLKSPD_DIV_32 (0x05) +#define CLKSPD_DIV_64 (0x06) +#define CLKSPD_DIV_128 (0x07) + + + +/* + * Flash Controller + */ + +// FCTL (0xAE) - Flash Control +#define FCTL_BUSY 0x80 +#define FCTL_SWBSY 0x40 +#define FCTL_CONTRD 0x10 +#define FCTL_WRITE 0x02 +#define FCTL_ERASE 0x01 + + +// FWDATA (0xAF) - Flash Write Data + +// FADDRH (0xAD) - Flash Address High Byte + +// FADDRL (0xAC) - Flash Address Low Byte + +// FWT (0xAB) - Flash Write Timing (Only bit 0-5 R/W) + + +/* + * I/O Ports + */ + +// P0 (0x80) - Port 0 - bit accessible SFR register + +// P1 (0x90) - Port 1 - bit accessible SFR register + +// P2 (0xA0) - Port 2 - bit accessible SFR register + +// PERCFG (0xF1) - Peripheral Control +#define PERCFG_T1CFG 0x40 +#define PERCFG_T3CFG 0x20 +#define PERCFG_T4CFG 0x10 +#define PERCFG_U1CFG 0x02 +#define PERCFG_U0CFG 0x01 + + + +// ADCCFG (0xF2) - ADC input Configuration +#define ADCCFG_7 0x80 +#define ADCCFG_6 0x40 +#define ADCCFG_5 0x20 +#define ADCCFG_4 0x10 +#define ADCCFG_3 0x08 +#define ADCCFG_2 0x04 +#define ADCCFG_1 0x02 +#define ADCCFG_0 0x01 + + +// P0SEL (0xF3) - Port 0 Function Select (bit 7 not used) + +// P1SEL (0xF4) - Port 1 Function Select + +// P2SEL (0xF5) - Port 2 Function Select +#define P2SEL_PRI3P1 0x40 +#define P2SEL_PRI2P1 0x20 +#define P2SEL_PRI1P1 0x10 +#define P2SEL_PRI0P1 0x08 +#define P2SEL_SELP2_4 0x04 +#define P2SEL_SELP2_3 0x02 +#define P2SEL_SELP2_0 0x01 + + +// P0DIR (0xFD) - Port 0 Direction Select + +// P1DIR (0xFE) - Port 1 Direction Select + +// P2DIR (0xFF) - Port 2 Direction +#define P2DIR_PRIP0 0xC0 +#define P2DIR_0PRIP0 0x40 +#define P2DIR_1PRIP0 0x80 +#define P2DIR_DIRP2 0x1F + +#define P2DIR_PRIP0_0 (0x00 << 6) +#define P2DIR_PRIP0_1 (0x01 << 6) +#define P2DIR_PRIP0_2 (0x02 << 6) +#define P2DIR_PRIP0_3 (0x03 << 6) + +#define P2DIR_DIRP2_4 (0x10) +#define P2DIR_DIRP2_3 (0x08) +#define P2DIR_DIRP2_2 (0x04) +#define P2DIR_DIRP2_1 (0x02) +#define P2DIR_DIRP2_0 (0x01) + + + +// P0INP (0x8F) - Port 0 Input Mode (bit 0 & 1 not used) + +// P1INP (0xF6) - Port 1 Input Mode (bit 0 & 1 not used) + +// P2INP (0xF7) - Port 2 Input Mode +#define P2INP_PDUP2 0x80 +#define P2INP_PDUP1 0x40 +#define P2INP_PDUP0 0x20 +#define P2INP_MDP2 0x1F + +#define P2INP_MDP2_0 (0x01) +#define P2INP_MDP2_1 (0x02) +#define P2INP_MDP2_2 (0x04) +#define P2INP_MDP2_3 (0x08) +#define P2INP_MDP2_4 (0x10) + + + +// P0IFG (0x89) - Port 0 Interrupt Status Flag + +// P1IFG (0x8A) - Port 1 Interrupt Status Flag + +// P2IFG (0x8B) - Port 2 Interrupt Status Flag (bit 7 - 5 not used) + +// PICTL (0x8C) - Port Interrupt Control +#define PICTL_PADSC 0x40 +#define PICTL_P2IEN 0x20 +#define PICTL_P0IENH 0x10 +#define PICTL_P0IENL 0x08 +#define PICTL_P2ICON 0x04 +#define PICTL_P1ICON 0x02 +#define PICTL_P0ICON 0x01 + + +// P1IEN (0x8D) - Port 1 Interrupt Mask + + + +/* + * DMA Controller + */ + +// DMAARM (0xD6) - DMA Channel Arm +#define DMAARM_ABORT 0x80 +#define DMAARM4 0x10 +#define DMAARM3 0x08 +#define DMAARM2 0x04 +#define DMAARM1 0x02 +#define DMAARM0 0x01 + + +// DMAREQ (0xD7) - DMA Channel Start Request and Status +#define DMAREQ4 0x10 +#define DMAREQ3 0x08 +#define DMAREQ2 0x04 +#define DMAREQ1 0x02 +#define DMAREQ0 0x01 + + +// DMA0CFGH (0xD5) - DMA Channel 0 Configuration Address High Byte + +// DMA0CFGL (0xD4) - DMA Channel 0 Configuration Address Low Byte + +// DMA1CFGH (0xD3) - DMA Channel 1 - 4 Configuration Address High By + +// DMA1CFGL (0xD2) - DMA Channel 1 - 4 Configuration Address Low Byte + +// DMAIRQ (0xD1) - DMA Interrupt Flag +#define DMAIRQ_DMAIF4 0x10 +#define DMAIRQ_DMAIF3 0x08 +#define DMAIRQ_DMAIF2 0x04 +#define DMAIRQ_DMAIF1 0x02 +#define DMAIRQ_DMAIF0 0x01 + + +// T1CNTH (0xE3) - Timer 1 Counter High + +// T1CNTL (0xE2) - Timer 1 Counter Low + +// T1CTL (0xE4) - Timer 1 Control and Status +#define T1CTL_CH2IF 0x80 // Timer 1 channel 2 interrupt flag +#define T1CTL_CH1IF 0x40 // Timer 1 channel 1 interrupt flag +#define T1CTL_CH0IF 0x20 // Timer 1 channel 0 interrupt flag +#define T1CTL_OVFIF 0x10 // Timer 1 counter overflow interrupt flag +#define T1CTL_DIV 0x0C +#define T1CTL_DIV0 0x04 +#define T1CTL_DIV1 0x08 +#define T1CTL_MODE 0x03 +#define T1CTL_MODE0 0x01 +#define T1CTL_MODE1 0x02 + +#define T1CTL_DIV_1 (0x00 << 2) // Divide tick frequency by 1 +#define T1CTL_DIV_8 (0x01 << 2) // Divide tick frequency by 8 +#define T1CTL_DIV_32 (0x02 << 2) // Divide tick frequency by 32 +#define T1CTL_DIV_128 (0x03 << 2) // Divide tick frequency by 128 + +#define T1CTL_MODE_SUSPEND (0x00) // Operation is suspended (halt) +#define T1CTL_MODE_FREERUN (0x01) // Free Running mode +#define T1CTL_MODE_MODULO (0x02) // Modulo +#define T1CTL_MODE_UPDOWN (0x03) // Up/down + + +// T1CCTL0 (0xE5) - Timer 1 Channel 0 Capture/Compare Control +#define T1CCTL0_CPSEL 0x80 // Timer 1 channel 0 capture select +#define T1CCTL0_IM 0x40 // Channel 0 Interrupt mask +#define T1CCTL0_CMP 0x38 +#define T1CCTL0_CMP0 0x08 +#define T1CCTL0_CMP1 0x10 +#define T1CCTL0_CMP2 0x20 +#define T1CCTL0_MODE 0x04 // Capture or compare mode +#define T1CCTL0_CAP 0x03 +#define T1CCTL0_CAP0 0x01 +#define T1CCTL0_CAP1 0x02 + +#define T1C0_SET_ON_CMP (0x00 << 3) // Clear output on compare-up set on 0 +#define T1C0_CLR_ON_CMP (0x01 << 3) // Set output on compare-up clear on 0 +#define T1C0_TOG_ON_CMP (0x02 << 3) // Toggle output on compare +#define T1C0_SET_CMP_UP_CLR_0 (0x03 << 3) // Clear output on compare +#define T1C0_CLR_CMP_UP_SET_0 (0x04 << 3) // Set output on compare + +#define T1C0_NO_CAP (0x00) // No capture +#define T1C0_RISE_EDGE (0x01) // Capture on rising edge +#define T1C0_FALL_EDGE (0x02) // Capture on falling edge +#define T1C0_BOTH_EDGE (0x03) // Capture on both edges + + +// T1CC0H (0xDB) - Timer 1 Channel 0 Capture/Compare Value High + +// T1CC0L (0xDA) - Timer 1 Channel 0 Capture/Compare Value Low + +// T1CCTL1 (0xE6) - Timer 1 Channel 1 Capture/Compare Control +#define T1CCTL1_CPSEL 0x80 // Timer 1 channel 1 capture select +#define T1CCTL1_IM 0x40 // Channel 1 Interrupt mask +#define T1CCTL1_CMP 0x38 +#define T1CCTL1_CMP0 0x08 +#define T1CCTL1_CMP1 0x10 +#define T1CCTL1_CMP2 0x20 +#define T1CCTL1_MODE 0x04 // Capture or compare mode +#define T1CCTL1_DSM_SPD 0x04 +#define T1CCTL1_CAP 0x03 +#define T1CCTL1_CAP0 0x01 +#define T1CCTL1_CAP1 0x02 + +#define T1C1_SET_ON_CMP (0x00 << 3) // Set output on compare +#define T1C1_CLR_ON_CMP (0x01 << 3) // Clear output on compare +#define T1C1_TOG_ON_CMP (0x02 << 3) // Toggle output on compare +#define T1C1_SET_CMP_UP_CLR_0 (0x03 << 3) // Set output on compare-up clear on 0 +#define T1C1_CLR_CMP_UP_SET_0 (0x04 << 3) // Clear output on compare-up set on 0 +#define T1C1_SET_C1_CLR_C0 (0x05 << 3) // Set when equal to T1CC1, clear when equal to T1CC0 +#define T1C1_CLR_C1_SET_C0 (0x06 << 3) // Clear when equal to T1CC1, set when equal to T1CC0 +#define T1C1_DSM_MODE (0x07 << 3) // DSM mode + +#define T1C1_NO_CAP (0x00) // No capture +#define T1C1_RISE_EDGE (0x01) // Capture on rising edge +#define T1C1_FALL_EDGE (0x02) // Capture on falling edge +#define T1C1_BOTH_EDGE (0x03) // Capture on both edges + +#define DSM_IP_ON_OS_ON (0x00) // Interpolator & output shaping enabled +#define DSM_IP_ON_OS_OFF (0x01) // Interpolator enabled & output shaping disabled +#define DSM_IP_OFF_OS_ON (0x02) // Interpolator disabled & output shaping enabled +#define DSM_IP_OFF_OS_OFF (0x03) // Interpolator & output shaping disabled + + + +// T1CC1H (0xDD) - Timer 1 Channel 1 Capture/Compare Value High + +// T1CC1L (0xDC) - Timer 1 Channel 1 Capture/Compare Value Low + +// T1CCTL2 (0xE7) - Timer 1 Channel 2 Capture/Compare Control +#define T1CCTL2_CPSEL 0x80 // Timer 1 channel 2 capture select +#define T1CCTL2_IM 0x40 // Channel 2 Interrupt mask +#define T1CCTL2_CMP 0x38 +#define T1CCTL2_CMP0 0x08 +#define T1CCTL2_CMP1 0x10 +#define T1CCTL2_CMP2 0x20 +#define T1CCTL2_MODE 0x04 // Capture or compare mode +#define T1CCTL2_CAP 0x03 +#define T1CCTL2_CAP0 0x01 +#define T1CCTL2_CAP1 0x02 + +#define T1C2_SET_ON_CMP (0x00 << 3) // Set output on compare +#define T1C2_CLR_ON_CMP (0x01 << 3) // Clear output on compare +#define T1C2_TOG_ON_CMP (0x02 << 3) // Toggle output on compare +#define T1C2_SET_CMP_UP_CLR_0 (0x03 << 3) // Set output on compare-up clear on 0 +#define T1C2_CLR_CMP_UP_SET_0 (0x04 << 3) // Clear output on compare-up set on 0 +#define T1C2_SET_C2_CLR_C0 (0x05 << 3) // Set when equal to T1CC2, clear when equal to T1CC0 +#define T1C2_CLR_C2_SET_C0 (0x06 << 3) // Clear when equal to T1CC2, set when equal to T1CC0 + +#define T1C2_NO_CAP (0x00) // No capture +#define T1C2_RISE_EDGE (0x01) // Capture on rising edge +#define T1C2_FALL_EDGE (0x02) // Capture on falling edge +#define T1C2_BOTH_EDGE (0x03) // Capture on both edges + + +// T1CC2H (0xDF) - Timer 1 Channel 2 Capture/Compare Value High + +// T1CC2L (0xDE) - Timer 1 Channel 2 Capture/Compare Value Low + +// T2CTL (0x9E) - Timer 2 Control +#define T2CTL_TEX 0x40 +#define T2CTL_INT 0x10 // Enable Timer 2 interrupt +#define T2CTL_TIG 0x04 // Tick generator mode +#define T2CTL_TIP 0x03 +#define T2CTL_TIP0 0x01 +#define T2CTL_TIP1 0x02 + +#define T2CTL_TIP_64 (0x00) +#define T2CTL_TIP_128 (0x01) +#define T2CTL_TIP_256 (0x02) +#define T2CTL_TIP_1024 (0x03) + + +// T2CT (0x9C) - Timer 2 Count + +// T2PR (0x9D) - Timer 2 Prescaler + +// WORTIME0 (0xA5) - Sleep Timer Low Byte + +// WORTIME1 (0xA6) - Sleep Timer High Byte + +// WOREVT1 (0xA4) - Sleep Timer Event0 Timeout High + +// WOREVT0 (0xA3) - Sleep Timer Event0 Timeout Low + +// WORCTL (0xA2) - Sleep Timer Control +#define WORCTL_WOR_RESET 0x04 +#define WORCTL_WOR_RES 0x03 +#define WORCTL_WOR_RES0 0x01 +#define WORCTL_WOR_RES1 0x02 + +#define WORCTL_WOR_RES_1 (0x00) +#define WORCTL_WOR_RES_32 (0x01) +#define WORCTL_WOR_RES_1024 (0x02) +#define WORCTL_WOR_RES_32768 (0x03) + + +// WORIRQ (0xA1) - Sleep Timer Interrupt Control +#define WORIRQ_EVENT0_MASK 0x10 +#define WORIRQ_EVENT0_FLAG 0x01 + + +// T3CNT (0xCA) - Timer 3 Counter + +// T3CTL (0xCB) - Timer 3 Control +#define T3CTL_DIV 0xE0 +#define T3CTL_DIV0 0x20 +#define T3CTL_DIV1 0x40 +#define T3CTL_DIV2 0x80 +#define T3CTL_START 0x10 +#define T3CTL_OVFIM 0x08 +#define T3CTL_CLR 0x04 +#define T3CTL_MODE 0x03 +#define T3CTL_MODE0 0x01 +#define T3CTL_MODE1 0x02 + +#define T3CTL_DIV_1 (0x00 << 5) +#define T3CTL_DIV_2 (0x01 << 5) +#define T3CTL_DIV_4 (0x02 << 5) +#define T3CTL_DIV_8 (0x03 << 5) +#define T3CTL_DIV_16 (0x04 << 5) +#define T3CTL_DIV_32 (0x05 << 5) +#define T3CTL_DIV_64 (0x06 << 5) +#define T3CTL_DIV_128 (0x07 << 5) + +#define T3CTL_MODE_FREERUN (0x00) +#define T3CTL_MODE_DOWN (0x01) +#define T3CTL_MODE_MODULO (0x02) +#define T3CTL_MODE_UPDOWN (0x03) + + + +// T3CCTL0 (0xCC) - Timer 3 Channel 0 Compare Control +#define T3CCTL0_IM 0x40 +#define T3CCTL0_MODE 0x04 +#define T3CCTL0_CMP 0x38 +#define T3CCTL0_CMP0 0x08 +#define T3CCTL0_CMP1 0x10 +#define T3CCTL0_CMP2 0x20 + +#define T3C0_SET_ON_CMP (0x00 << 3) // Set output on compare +#define T3C0_CLR_ON_CMP (0x01 << 3) // Clear output on compare +#define T3C0_TOG_ON_CMP (0x02 << 3) // Toggle output on compare +#define T3C0_SET_CMP_UP_CLR_0 (0x03 << 3) // Set output on compare-up clear on 0 +#define T3C0_CLR_CMP_UP_SET_0 (0x04 << 3) // Clear output on compare-up set on 0 +#define T3C0_SET_CMP_CLR_255 (0x05 << 3) // Set when equal to T3CC0, clear on 255 +#define T3C0_CLR_CMP_SET_0 (0x06 << 3) // Clear when equal to T3CC0, set on 0 + + + +// T3CC0 (0xCD) - Timer 3 Channel 0 Compare Value + +// T3CCTL1 (0xCE) - Timer 3 Channel 1 Compare Control + +#define T3CCTL1_IM 0x40 +#define T3CCTL1_MODE 0x04 +#define T3CCTL1_CMP 0x38 +#define T3CCTL1_CMP0 0x08 +#define T3CCTL1_CMP1 0x10 +#define T3CCTL1_CMP2 0x20 + +#define T3C1_SET_ON_CMP (0x00 << 3) // Set output on compare +#define T3C1_CLR_ON_CMP (0x01 << 3) // Clear output on compare +#define T3C1_TOG_ON_CMP (0x02 << 3) // Toggle output on compare +#define T3C1_SET_CMP_UP_CLR_0 (0x03 << 3) // Set output on compare-up clear on 0 +#define T3C1_CLR_CMP_UP_SET_0 (0x04 << 3) // Clear output on compare-up set on 0 +#define T3C1_SET_CMP_CLR_C0 (0x05 << 3) // Set when equal to T3CC1, clear when equal to T3CC0 +#define T3C1_CLR_CMP_SET_C0 (0x06 << 3) // Clear when equal to T3CC1, set when equal to T3CC0 + + +// T3CC1 (0xCF) - Timer 3 Channel 1 Compare Value + +// T4CNT (0xEA) - Timer 4 Counter + +// T4CTL (0xEB) - Timer 4 Control +#define T4CTL_DIV 0xE0 +#define T4CTL_DIV0 0x20 +#define T4CTL_DIV1 0x40 +#define T4CTL_DIV2 0x80 +#define T4CTL_START 0x10 +#define T4CTL_OVFIM 0x08 +#define T4CTL_CLR 0x04 +#define T4CTL_MODE 0x03 +#define T4CTL_MODE0 0x01 +#define T4CTL_MODE1 0x02 + +#define T4CTL_MODE_FREERUN (0x00) +#define T4CTL_MODE_DOWN (0x01) +#define T4CTL_MODE_MODULO (0x02) +#define T4CTL_MODE_UPDOWN (0x03) + +#define T4CTL_DIV_1 (0x00 << 5) +#define T4CTL_DIV_2 (0x01 << 5) +#define T4CTL_DIV_4 (0x02 << 5) +#define T4CTL_DIV_8 (0x03 << 5) +#define T4CTL_DIV_16 (0x04 << 5) +#define T4CTL_DIV_32 (0x05 << 5) +#define T4CTL_DIV_64 (0x06 << 5) +#define T4CTL_DIV_128 (0x07 << 5) + + +// T4CCTL0 (0xEC) - Timer 4 Channel 0 Compare Control +#define T4CCTL0_IM 0x40 +#define T4CCTL0_CMP 0x38 +#define T4CCTL0_CMP0 0x08 +#define T4CCTL0_CMP1 0x10 +#define T4CCTL0_CMP2 0x20 +#define T4CCTL0_MODE 0x04 + +#define T4CCTL0_SET_ON_CMP (0x00 << 3) +#define T4CCTL0_CLR_ON_CMP (0x01 << 3) +#define T4CCTL0_TOG_ON_CMP (0x02 << 3) +#define T4CCTL0_SET_CMP_UP_CLR_0 (0x03 << 3) +#define T4CCTL0_CLR_CMP_UP_SET_0 (0x04 << 3) +#define T4CCTL0_SET_CMP_CLR_255 (0x05 << 3) +#define T4CCTL0_CLR_CMP_SET_0 (0x06 << 3) + + +// T4CC0 (0xED) - Timer 4 Channel 0 Compare Value + +// T4CCTL1 (0xEE) - Timer 4 Channel 1 Compare Control +#define T4CCTL1_IM 0x40 +#define T4CCTL1_CMP 0x38 +#define T4CCTL1_CMP0 0x08 +#define T4CCTL1_CMP1 0x10 +#define T4CCTL1_CMP2 0x20 +#define T4CCTL1_MODE 0x04 + +#define T4CCTL1_SET_ON_CMP (0x00 << 3) +#define T4CCTL1_CLR_ON_CMP (0x01 << 3) +#define T4CCTL1_TOG_ON_CMP (0x02 << 3) +#define T4CCTL1_SET_CMP_UP_CLR_0 (0x03 << 3) +#define T4CCTL1_CLR_CMP_UP_SET_0 (0x04 << 3) +#define T4CCTL1_SET_CMP_CLR_C0 (0x05 << 3) +#define T4CCTL1_CLR_CMP_SET_C0 (0x06 << 3) + + +// TIMIF (0xD8) - Timers 1/3/4 Interrupt Mask/Flag - bit accessible SFR register + + +/* + * ADC + */ + +// ADCL (0xBA) - ADC Data Low (only bit 7-4 used) + +// ADCH (0xBB) - ADC Data High + +// ADCCON1 (0xB4) - ADC Control 1 +#define ADCCON1_EOC 0x80 +#define ADCCON1_ST 0x40 +#define ADCCON1_STSEL 0x30 +#define ADCCON1_STSEL0 0x10 +#define ADCCON1_STSEL1 0x20 +#define ADCCON1_RCTRL 0x0C +#define ADCCON1_RCTRL0 0x04 +#define ADCCON1_RCTRL1 0x08 + +#define STSEL_P2_0 (0x00 << 4) +#define STSEL_FULL_SPEED (0x01 << 4) +#define STSEL_T1C0_CMP_EVT (0x02 << 4) +#define STSEL_ST (0x03 << 4) + +#define ADCCON1_RCTRL_COMPL (0x00 << 2) +#define ADCCON1_RCTRL_LFSR13 (0x01 << 2) + + + +// ADCCON2 (0xB5) - ADC Control 2 +#define ADCCON2_SREF 0xC0 +#define ADCCON2_SREF0 0x40 +#define ADCCON2_SREF1 0x80 +#define ADCCON2_SDIV 0x30 +#define ADCCON2_SDIV0 0x10 +#define ADCCON2_SDIV1 0x20 +#define ADCCON2_SCH 0x0F +#define ADCCON2_SCH0 0x01 +#define ADCCON2_SCH1 0x02 +#define ADCCON2_SCH2 0x04 +#define ADCCON2_SCH3 0x08 + +#define ADCCON2_SREF_1_25V (0x00 << 6) +#define ADCCON2_SREF_P0_7 (0x01 << 6) +#define ADCCON2_SREF_AVDD (0x02 << 6) +#define ADCCON2_SREF_P0_6_P0_7 (0x03 << 6) + +#define ADCCON2_SDIV_64 (0x00 << 4) +#define ADCCON2_SDIV_128 (0x01 << 4) +#define ADCCON2_SDIV_256 (0x02 << 4) +#define ADCCON2_SDIV_512 (0x03 << 4) + +#define ADCCON2_SCH_AIN0 (0x00) +#define ADCCON2_SCH_AIN1 (0x01) +#define ADCCON2_SCH_AIN2 (0x02) +#define ADCCON2_SCH_AIN3 (0x03) +#define ADCCON2_SCH_AIN4 (0x04) +#define ADCCON2_SCH_AIN5 (0x05) +#define ADCCON2_SCH_AIN6 (0x06) +#define ADCCON2_SCH_AIN7 (0x07) +#define ADCCON2_SCH_AIN0_1 (0x08) +#define ADCCON2_SCH_AIN2_3 (0x09) +#define ADCCON2_SCH_AIN4_5 (0x0A) +#define ADCCON2_SCH_AIN6_7 (0x0B) +#define ADCCON2_SCH_GND (0x0C) +#define ADCCON2_SCH_POSVOL (0x0D) +#define ADCCON2_SCH_TEMPR (0x0E) +#define ADCCON2_SCH_VDD_3 (0x0F) + + +// ADCCON3 (0xB6) - ADC Control 3 +#define ADCCON3_EREF 0xC0 +#define ADCCON3_EREF0 0x40 +#define ADCCON3_EREF1 0x80 +#define ADCCON3_EDIV 0x30 +#define ADCCON3_EDIV0 0x10 +#define ADCCON3_EDIV1 0x20 +#define ADCCON2_ECH 0x0F +#define ADCCON2_ECH0 0x01 +#define ADCCON2_ECH1 0x02 +#define ADCCON2_ECH2 0x04 +#define ADCCON2_ECH3 0x08 + +#define ADCCON3_EREF_1_25V (0x00 << 6) +#define ADCCON3_EREF_P0_7 (0x01 << 6) +#define ADCCON3_EREF_AVDD (0x02 << 6) +#define ADCCON3_EREF_P0_6_P0_7 (0x03 << 6) + +#define ADCCON3_EDIV_64 (0x00 << 4) +#define ADCCON3_EDIV_128 (0x01 << 4) +#define ADCCON3_EDIV_256 (0x02 << 4) +#define ADCCON3_EDIV_512 (0x03 << 4) + +#define ADCCON3_ECH_AIN0 (0x00) +#define ADCCON3_ECH_AIN1 (0x01) +#define ADCCON3_ECH_AIN2 (0x02) +#define ADCCON3_ECH_AIN3 (0x03) +#define ADCCON3_ECH_AIN4 (0x04) +#define ADCCON3_ECH_AIN5 (0x05) +#define ADCCON3_ECH_AIN6 (0x06) +#define ADCCON3_ECH_AIN7 (0x07) +#define ADCCON3_ECH_AIN0_1 (0x08) +#define ADCCON3_ECH_AIN2_3 (0x09) +#define ADCCON3_ECH_AIN4_5 (0x0A) +#define ADCCON3_ECH_AIN6_7 (0x0B) +#define ADCCON3_ECH_GND (0x0C) +#define ADCCON3_ECH_POSVOL (0x0D) +#define ADCCON3_ECH_TEMPR (0x0E) +#define ADCCON3_ECH_VDD_3 (0x0F) + + + +/* + * Random Number Generator + */ + +// RNDL (0xBC) - Random Number Generator Data Low Byte + +// RNDH (0xBD) - Random Number Generator Data High Byte + + +/* + * AES + */ + +// ENCCS (0xB3) - Encryption Control and Status +#define ENCCS_MODE 0x70 +#define ENCCS_MODE0 0x10 +#define ENCCS_MODE1 0x20 +#define ENCCS_MODE2 0x40 +#define ENCCS_RDY 0x08 +#define ENCCS_CMD 0x06 +#define ENCCS_CMD0 0x02 +#define ENCCS_CMD1 0x04 +#define ENCCS_ST 0x01 + +#define ENCCS_MODE_CBC (0x00 << 4) +#define ENCCS_MODE_CFB (0x01 << 4) +#define ENCCS_MODE_OFB (0x02 << 4) +#define ENCCS_MODE_CTR (0x03 << 4) +#define ENCCS_MODE_ECB (0x04 << 4) +#define ENCCS_MODE_CBCMAC (0x05 << 4) + +#define ENCCS_CMD_ENC (0x00 << 1) +#define ENCCS_CMD_DEC (0x01 << 1) +#define ENCCS_CMD_LDKEY (0x02 << 1) +#define ENCCS_CMD_LDIV (0x03 << 1) + + +// ENCDI (0xB1) - Encryption Input Data + +// ENCDO (0xB2) - Encryption Output Data + + +/* + * Watchdog Timer + */ + +// WDCTL (0xC9) - Watchdog Timer Control +#define WDCTL_CLR 0xF0 +#define WDCTL_CLR0 0x10 +#define WDCTL_CLR1 0x20 +#define WDCTL_CLR2 0x40 +#define WDCTL_CLR3 0x80 +#define WDCTL_EN 0x08 +#define WDCTL_MODE 0x04 +#define WDCTL_INT 0x03 +#define WDCTL_INT0 0x01 +#define WDCTL_INT1 0x02 + + +#define WDCTL_INT_SEC_1 (0x00) +#define WDCTL_INT1_MSEC_250 (0x01) +#define WDCTL_INT2_MSEC_15 (0x02) +#define WDCTL_INT3_MSEC_2 (0x03) + + + +/* + * USART + */ + +// U0CSR (0x86) - USART 0 Control and Status + +#define U0CSR_MODE 0x80 +#define U0CSR_RE 0x40 +#define U0CSR_SLAVE 0x20 +#define U0CSR_FE 0x10 +#define U0CSR_ERR 0x08 +#define U0CSR_RX_BYTE 0x04 +#define U0CSR_TX_BYTE 0x02 +#define U0CSR_ACTIVE 0x01 + + +// U0UCR (0xC4) - USART 0 UART Control +#define U0UCR_FLUSH 0x80 +#define U0UCR_FLOW 0x40 +#define U0UCR_D9 0x20 +#define U0UCR_BIT9 0x10 +#define U0UCR_PARITY 0x08 +#define U0UCR_SPB 0x04 +#define U0UCR_STOP 0x02 +#define U0UCR_START 0x01 + + +// U0GCR (0xC5) - USART 0 Generic Control +#define U0GCR_CPOL 0x80 +#define U0GCR_CPHA 0x40 +#define U0GCR_ORDER 0x20 +#define U0GCR_BAUD_E 0x1F +#define U0GCR_BAUD_E0 0x01 +#define U0GCR_BAUD_E1 0x02 +#define U0GCR_BAUD_E2 0x04 +#define U0GCR_BAUD_E3 0x08 +#define U0GCR_BAUD_E4 0x10 + + +// U0DBUF (0xC1) - USART 0 Receive/Transmit Data Buffer + +// U0BAUD (0xC2) - USART 0 Baud Rate Control + +// U1CSR (0xF8) - USART 1 Control and Status - bit accessible SFR register +#define U1CSR_MODE 0x80 +#define U1CSR_RE 0x40 +#define U1CSR_SLAVE 0x20 +#define U1CSR_FE 0x10 +#define U1CSR_ERR 0x08 +#define U1CSR_RX_BYTE 0x04 +#define U1CSR_TX_BYTE 0x02 +#define U1CSR_ACTIVE 0x01 + + +// U1UCR (0xFB) - USART 1 UART Control +#define U1UCR_FLUSH 0x80 +#define U1UCR_FLOW 0x40 +#define U1UCR_D9 0x20 +#define U1UCR_BIT9 0x10 +#define U1UCR_PARITY 0x08 +#define U1UCR_SPB 0x04 +#define U1UCR_STOP 0x02 +#define U1UCR_START 0x01 + + +// U1GCR (0xFC) - USART 1 Generic Control +#define U1GCR_CPOL 0x80 +#define U1GCR_CPHA 0x40 +#define U1GCR_ORDER 0x20 +#define U1GCR_BAUD_E 0x1F +#define U1GCR_BAUD_E0 0x01 +#define U1GCR_BAUD_E1 0x02 +#define U1GCR_BAUD_E2 0x04 +#define U1GCR_BAUD_E3 0x08 +#define U1GCR_BAUD_E4 0x10 + + +// U1DBUF (0xF9) - USART 1 Receive/Transmit Data Buffer + +// U1BAUD (0xFA) - USART 1 Baud Rate Control + + +/* + * I2S + */ + +// 0xDF40: I2SCFG0 - I2S Configuration Register 0 +#define I2SCFG0_TXIEN 0x80 +#define I2SCFG0_RXIEN 0x40 +#define I2SCFG0_ULAWE 0x20 +#define I2SCFG0_ULAWC 0x10 +#define I2SCFG0_TXMONO 0x08 +#define I2SCFG0_RXMONO 0x04 +#define I2SCFG0_MASTER 0x02 +#define I2SCFG0_ENAB 0x01 + + +// 0xDF41: I2SCFG1 - I2S Configuration Register 1 +#define I2SCFG1_WORDS 0xF8 +#define I2SCFG1_WORDS0 0x08 +#define I2SCFG1_WORDS1 0x10 +#define I2SCFG1_WORDS2 0x20 +#define I2SCFG1_WORDS3 0x40 +#define I2SCFG1_WORDS4 0x80 +#define I2SCFG1_TRIGNUM 0x06 +#define I2SCFG1_TRIGNUM0 0x02 +#define I2SCFG1_TRIGNUM1 0x04 +#define I2SCFG1_IOLOC 0x01 + +#define I2SCFG1_TRIGNUM_NO_TRIG (0x00 << 1) +#define I2SCFG1_TRIGNUM_USB_SOF (0x01 << 1) +#define I2SCFG1_TRIGNUM_IOC_1 (0x02 << 1) +#define I2SCFG1_TRIGNUM_T1_CH0 (0x03 << 1) + + + +// 0xDF42: I2SDATL - I2S Data Low Byte + +// 0xDF43: I2SDATH - I2S Data High Byte + +// 0xDF44: I2SWCNT - I2S Word Count Register + +// 0xDF45: I2SSTAT - I2S Status Register +#define I2SSTAT_TXUNF 0x80 +#define I2SSTAT_RXOVF 0x40 +#define I2SSTAT_TXLR 0x20 +#define I2SSTAT_RXLR 0x10 +#define I2SSTAT_TXIRQ 0x08 +#define I2SSTAT_RXIRQ 0x04 +#define I2SSTAT_WCNT 0x03 +#define I2SSTAT_WCNT0 0x01 +#define I2SSTAT_WCNT1 0x02 + +#define I2SSTAT_WCNT_10BIT (0x02) +#define I2SSTAT_WCNT_9BIT (0x01) +#define I2SSTAT_WCNT_9_10BIT (0x02) + + +// 0xDF46: I2SCLKF0 - I2S Clock Configuration Register 0 + +// 0xDF47: I2SCLKF1 - I2S Clock Configuration Register 1 + +// 0xDF48: I2SCLKF2 - I2S Clock Configuration Register 2 + + + + +/* + * Radio Registers + */ + +// RFIF (0xE9) - RF Interrupt Flags +#define RFIF_IRQ_TXUNF 0x80 +#define RFIF_IRQ_RXOVF 0x40 +#define RFIF_IRQ_TIMEOUT 0x20 +#define RFIF_IRQ_DONE 0x10 +#define RFIF_IRQ_CS 0x08 +#define RFIF_IRQ_PQT 0x04 +#define RFIF_IRQ_CCA 0x02 +#define RFIF_IRQ_SFD 0x01 + + +// RFIM (0x91) - RF Interrupt Mask +#define RFIM_IM_TXUNF 0x80 +#define RFIM_IM_RXOVF 0x40 +#define RFIM_IM_TIMEOUT 0x20 +#define RFIM_IM_DONE 0x10 +#define RFIM_IM_CS 0x08 +#define RFIM_IM_PQT 0x04 +#define RFIM_IM_CCA 0x02 +#define RFIM_IM_SFD 0x01 + + +// 0xDF2F: IOCFG2 - Radio Test Signal Configuration (P1_7) +#define IOCFG2_GDO2_INV 0x40 +#define IOCFG2_GDO2_CFG 0x3F + + +// 0xDF30: IOCFG1 - Radio Test Signal Configuration (P1_6) +#define IOCFG1_GDO_DS 0x80 +#define IOCFG1_GDO1_INV 0x40 +#define IOCFG1_GDO1_CFG 0x3F + + +// 0xDF31: IOCFG0 - Radio Test Signal Configuration (P1_5) +#define IOCFG0_GDO0_INV 0x40 +#define IOCFG0_GDO0_CFG 0x3F + + +// 0xDF03: PKTCTRL1 - Packet Automation Control +#define PKTCTRL1_PQT 0xE0 +#define PKTCTRL1_PQT0 0x20 +#define PKTCTRL1_PQT1 0x40 +#define PKTCTRL1_PQT2 0x80 +#define PKTCTRL1_APPEND_STATUS 0x04 +#define PKTCTRL1_ADR_CHK 0x03 +#define PKTCTRL1_ADR_CHK0 0x01 +#define PKTCTRL1_ADR_CHK1 0x02 + +#define ADR_CHK_NONE (0x00) +#define ADR_CHK_NO_BRDCST (0x01) +#define ADR_CHK_0_BRDCST (0x02) +#define ADR_CHK_0_255_BRDCST (0x03) + + +// 0xDF04: PKTCTRL0 - Packet Automation Control +#define PKTCTRL0_WHITE_DATA 0x40 +#define PKTCTRL0_PKT_FORMAT 0x30 +#define PKTCTRL0_PKT_FORMAT0 0x10 +#define PKTCTRL0_PKT_FORMAT1 0x20 +#define PKTCTRL0_CC2400_EN 0x08 +#define PKTCTRL0_CRC_EN 0x04 +#define PKTCTRL0_LENGTH_CONFIG 0x03 +#define PKTCTRL0_LENGTH_CONFIG0 0x01 + +#define PKT_FORMAT_NORM (0x00) +#define PKT_FORMAT_RAND (0x02) + +#define PKTCTRL0_LENGTH_CONFIG_FIX (0x00) +#define PKTCTRL0_LENGTH_CONFIG_VAR (0x01) + + +// 0xDF05: ADDR - Device Address + +// 0xDF06: CHANNR - Channel Number + +// 0xDF07: FSCTRL1 - Frequency Synthesizer Control (only bit 0-4 used) + +// 0xDF08: FSCTRL0 - Frequency Synthesizer Control + +// 0xDF09: FREQ2 - Frequency Control Word, High Byte + +// 0xDF0A: FREQ1 - Frequency Control Word, Middle Byte + +// 0xDF0B: FREQ0 - Frequency Control Word, Low Byte + +// 0xDF0C: MDMCFG4 - Modem configuration + +// 0xDF0D: MDMCFG3 - Modem Configuration + +// 0xDF0E: MDMCFG2 - Modem Configuration +#define MDMCFG2_DEM_DCFILT_OFF 0x80 +#define MDMCFG2_MOD_FORMAT 0x70 +#define MDMCFG2_MOD_FORMAT0 0x10 +#define MDMCFG2_MOD_FORMAT1 0x20 +#define MDMCFG2_MOD_FORMAT2 0x40 +#define MDMCFG2_MANCHESTER_EN 0x08 +#define MDMCFG2_SYNC_MODE 0x07 +#define MDMCFG2_SYNC_MODE0 0x01 +#define MDMCFG2_SYNC_MODE1 0x02 +#define MDMCFG2_SYNC_MODE2 0x04 + +#define MOD_FORMAT_2_FSK (0x00 << 4) +#define MOD_FORMAT_GFSK (0x01 << 4) +#define MOD_FORMAT_MSK (0x07 << 4) + +#define SYNC_MODE_NO_PRE (0x00) +#define SYNC_MODE_15_16 (0x01) +#define SYNC_MODE_16_16 (0x02) +#define SYNC_MODE_30_32 (0x03) +#define SYNC_MODE_NO_PRE_CS (0x04) // CS = carrier-sense above threshold +#define SYNC_MODE_15_16_CS (0x05) +#define SYNC_MODE_16_16_CS (0x06) +#define SYNC_MODE_30_32_CS (0x07) + + +// 0xDF0F: MDMCG1 - Modem Configuration +#define MDMCG1_FEC_EN 0x80 +#define MDMCG1_NUM_PREAMBLE 0x70 +#define MDMCG1_NUM_PREAMBLE0 0x10 +#define MDMCG1_NUM_PREAMBLE1 0x20 +#define MDMCG1_NUM_PREAMBLE2 0x40 +#define MDMCG1_CHANSPC_E 0x03 +#define MDMCG1_CHANSPC_E0 0x01 +#define MDMCG1_CHANSPC_E1 0x02 + +#define MDMCG1_NUM_PREAMBLE_2 (0x00 << 4) +#define MDMCG1_NUM_PREAMBLE_3 (0x01 << 4) +#define MDMCG1_NUM_PREAMBLE_4 (0x02 << 4) +#define MDMCG1_NUM_PREAMBLE_6 (0x03 << 4) +#define MDMCG1_NUM_PREAMBLE_8 (0x04 << 4) +#define MDMCG1_NUM_PREAMBLE_12 (0x05 << 4) +#define MDMCG1_NUM_PREAMBLE_16 (0x06 << 4) +#define MDMCG1_NUM_PREAMBLE_24 (0x07 << 4) + + +// 0xDF10: MDMCFG0 - Modem Configuration + +// 0xDF11: DEVIATN - Modem Deviation Setting +#define DEVIATN_DEVIATION_E 0x70 +#define DEVIATN_DEVIATION_E0 0x10 +#define DEVIATN_DEVIATION_E1 0x20 +#define DEVIATN_DEVIATION_E2 0x40 +#define DEVIATN_DEVIATION_M 0x07 +#define DEVIATN_DEVIATION_M0 0x01 +#define DEVIATN_DEVIATION_M1 0x02 +#define DEVIATN_DEVIATION_M2 0x04 + + +// 0xDF12: MCSM2 - Main Radio Control State Machine Configuration +#define MCSM2_RX_TIME_RSSI 0x10 +#define MCSM2_RX_TIME_QUAL 0x08 +#define MCSM2_RX_TIME 0x07 + + +// 0xDF13: MCSM1 - Main Radio Control State Machine Configuration +#define MCSM1_CCA_MODE 0x30 +#define MCSM1_CCA_MODE0 0x10 +#define MCSM1_CCA_MODE1 0x20 +#define MCSM1_RXOFF_MODE 0x0C +#define MCSM1_RXOFF_MODE0 0x04 +#define MCSM1_RXOFF_MODE1 0x08 +#define MCSM1_TXOFF_MODE 0x03 +#define MCSM1_TXOFF_MODE0 0x01 +#define MCSM1_TXOFF_MODE1 0x02 + +#define MCSM1_CCA_MODE_ALWAYS (0x00 << 4) +#define MCSM1_CCA_MODE_RSSI0 (0x01 << 4) +#define MCSM1_CCA_MODE_PACKET (0x02 << 4) +#define MCSM1_CCA_MODE_RSSI1 (0x03 << 4) + +#define MCSM1_RXOFF_MODE_IDLE (0x00 << 2) +#define MCSM1_RXOFF_MODE_FSTXON (0x01 << 2) +#define MCSM1_RXOFF_MODE_TX (0x02 << 2) +#define MCSM1_RXOFF_MODE_RX (0x03 << 2) + +#define MCSM1_TXOFF_MODE_IDLE (0x00 << 0) +#define MCSM1_TXOFF_MODE_FSTXON (0x01 << 0) +#define MCSM1_TXOFF_MODE_TX (0x02 << 0) +#define MCSM1_TXOFF_MODE_RX (0x03 << 0) + + +// 0xDF14: MCSM0 - Main Radio Control State Machine Configuration +#define MCSM0_FS_AUTOCAL 0x30 + +#define FS_AUTOCAL_NEVER (0x00 << 4) +#define FS_AUTOCAL_FROM_IDLE (0x01 << 4) +#define FS_AUTOCAL_TO_IDLE (0x02 << 4) +#define FS_AUTOCAL_4TH_TO_IDLE (0x03 << 4) + + +// 0xDF15: FOCCFG - Frequency Offset Compensation Configuration +#define FOCCFG_FOC_BS_CS_GATE 0x20 +#define FOCCFG_FOC_PRE_K 0x18 +#define FOCCFG_FOC_PRE_K0 0x08 +#define FOCCFG_FOC_PRE_K1 0x10 +#define FOCCFG_FOC_POST_K 0x04 +#define FOCCFG_FOC_LIMIT 0x03 +#define FOCCFG_FOC_LIMIT0 0x01 +#define FOCCFG_FOC_LIMIT1 0x02 + +#define FOC_PRE_K_1K (0x00 << 3) +#define FOC_PRE_K_2K (0x02 << 3) +#define FOC_PRE_K_3K (0x03 << 3) +#define FOC_PRE_K_4K (0x04 << 3) + +#define FOC_LIMIT_0 (0x00) +#define FOC_LIMIT_DIV8 (0x01) +#define FOC_LIMIT_DIV4 (0x02) +#define FOC_LIMIT_DIV2 (0x03) + + +// 0xDF16: BSCFG - Bit Synchronization Configuration +#define BSCFG_BS_PRE_KI 0xC0 +#define BSCFG_BS_PRE_KI0 0x40 +#define BSCFG_BS_PRE_KI1 0x80 +#define BSCFG_BS_PRE_KP 0x30 +#define BSCFG_BS_PRE_KP0 0x10 +#define BSCFG_BS_PRE_KP1 0x20 +#define BSCFG_BS_POST_KI 0x08 +#define BSCFG_BS_POST_KP 0x04 +#define BSCFG_BS_LIMIT 0x03 +#define BSCFG_BS_LIMIT0 0x01 +#define BSCFG_BS_LIMIT1 0x02 + +#define BSCFG_BS_PRE_KI_1K (0x00 << 6) +#define BSCFG_BS_PRE_KI_2K (0x01 << 6) +#define BSCFG_BS_PRE_KI_3K (0x02 << 6) +#define BSCFG_BS_PRE_KI_4K (0x03 << 6) + +#define BSCFG_BS_PRE_KP_1K (0x00 << 4) +#define BSCFG_BS_PRE_KP_2K (0x01 << 4) +#define BSCFG_BS_PRE_KP_3K (0x02 << 4) +#define BSCFG_BS_PRE_KP_4K (0x03 << 4) + +#define BSCFG_BS_LIMIT_0 (0x00) +#define BSCFG_BS_LIMIT_3 (0x01) +#define BSCFG_BS_LIMIT_6 (0x02) +#define BSCFG_BS_LIMIT_12 (0x03) + + +// 0xDF17: AGCCTRL2 - AGC Control +#define AGCCTRL2_MAX_DVGA_GAIN 0xC0 +#define AGCCTRL2_MAX_LNA_GAIN 0x38 +#define AGCCTRL2_MAGN_TARGET 0x07 + + +// 0xDF18: AGCCTRL1 - AGC Control +#define AGCCTRL1_AGC_LNA_PRIORITY 0x40 +#define AGCCTRL1_CARRIER_SENSE_REL_THR 0x30 +#define AGCCTRL1_CARRIER_SENSE_ABS_THR 0x0F + + +// 0xDF19: AGCCTRL0 - AGC Control +#define AGCCTRL0_HYST_LEVEL 0xC0 +#define AGCCTRL0_WAIT_TIME 0x30 +#define AGCCTRL0_AGC_FREEZE 0x0C +#define AGCCTRL0_FILTER_LENGTH 0x03 + + +// 0xDF1A: FREND1 - Front End RX Configuration +#define FREND1_LNA_CURRENT 0xC0 +#define FREND1_LNA2MIX_CURRENT 0x30 +#define FREND1_LODIV_BUF_CURRENT_RX 0x0C +#define FREND1_MIX_CURRENT 0x03 + + +// 0xDF1B: FREND0 - Front End TX Configuration +#define FREND0_LODIV_BUF_CURRENT_TX 0x30 + + +// 0xDF1C: FSCAL3 - Frequency Synthesizer Calibration +#define FSCAL3_FSCAL3 0xC0 +#define FSCAL3_CHP_CURR_CAL_EN 0x30 + + +// 0xDF1D: FSCAL2 - Frequency Synthesizer Calibration +#define FSCAL2_VCO_CORE_H_EN 0x20 +#define FSCAL2_FSCAL2 0x1F + + +// 0xDF1E: FSCAL1 - Frequency Synthesizer Calibration + +// 0xDF1F: FSCAL0 - Frequency Synthesizer Calibration + +// 0xDF25: TEST0 - Various Test Settings + + +// RFST (0xE1) - RF Strobe Commands +#define RFST_SFSTXON 0x00 +#define RFST_SCAL 0x01 +#define RFST_SRX 0x02 +#define RFST_STX 0x03 +#define RFST_SIDLE 0x04 +#define RFST_SNOP 0x05 + +// 0xDF3B: MARCSTATE - Main Radio Control State Machine State +#define MARCSTATE_MARC_STATE 0x1F + +#define MARC_STATE_SLEEP 0x00 +#define MARC_STATE_IDLE 0x01 +#define MARC_STATE_VCOON_MC 0x03 +#define MARC_STATE_REGON_MC 0x04 +#define MARC_STATE_MANCAL 0x05 +#define MARC_STATE_VCOON 0x06 +#define MARC_STATE_REGON 0x07 +#define MARC_STATE_STARTCAL 0x08 +#define MARC_STATE_BWBOOST 0x09 +#define MARC_STATE_FS_LOCK 0x0A +#define MARC_STATE_IFADCON 0x0B +#define MARC_STATE_ENDCAL 0x0C +#define MARC_STATE_RX 0x0D +#define MARC_STATE_RX_END 0x0E +#define MARC_STATE_RX_RST 0x0F +#define MARC_STATE_TXRX_SWITCH 0x10 +#define MARC_STATE_RX_OVERFLOW 0x11 +#define MARC_STATE_FSTXON 0x12 +#define MARC_STATE_TX 0x13 +#define MARC_STATE_TX_END 0x14 +#define MARC_STATE_RXTX_SWITCH 0x15 +#define MARC_STATE_TX_UNDERFLOW 0x16 + + +#endif diff --git a/boot/main.c b/cctl/main.c similarity index 100% rename from boot/main.c rename to cctl/main.c diff --git a/boot/start.asm b/cctl/start.asm similarity index 100% rename from boot/start.asm rename to cctl/start.asm